The present invention relates to a data processing system for vector processing which has a cache invalidation control unit for invalidating an address registered in a cache directory.
In a conventional data processing system having a store-through cache memory, data in a cache memory must be the same as data in a main memory. Particularly, for a cache memory control in a multiprocessor system wherein each processor has a cache memory and shares a single main memory with the other processors, a reference can be made to the paper entitled "Cache Memories" presented by ALAN JAY SMITH in "Computing Surveys," Vol. 14, No. 3, pp. 473-530, September, 1982. In the disclosed multiprocessor system, when a certain processor stores data in the main memory, the main memory address for the store operation is broadcast to all the other processors sharing the same main memory in the system. Then, each processor determines whether data associated with the store address is present in its cache memory. If data is present, the processor normally is required to invalidate that data in the cache, or else is required to update it to make it the same as the main memory data. A major difficulty in broadcasting store addresses lies in that every cache memory in the system is forced to surrender a cycle for invalidation lookup whenever any processor performs a store operation.
A system for fast and efficient cache invalidation control is disclosed in U.S. Pat. No. 4,142,234, for example. In accordance with that disclosed system, a buffer invalidation address stack (BIAS) filter memory is associated with each cache in a multiprocessor system. This filter memory serves to filter out repeated requests to invalidate the same block in a cache as disclosed in column 2 of the U.S. Pat. No. 4,142,234. This operation enhances the efficiency of invalidation. In this type of multiprocessor system, where a certain processor executes a move character instruction to store data in contiguous addresses of the main memory, invalidation requests associated with the contiguous addresses accumulate in the BIAS so that the filtering effect conforming to the block size of the cache memory may be expected. However, the problem with such a system is that since a store address is outputted from the BIAS in response to each store, difficulty is experienced in determining how long a store address should be held in the BIAS and how large the entry size of the BIAS should be. Another problem is that where data made up of a certain number of elements is to be stored in the addresses of the main memory at equal distances by a single instruction, or a parallel store is to be executed by increasing the number of interleaves of the main memory, it is necessary for the above-described system to collect invalidation addresses in parallel and such cannot be implemented without increasing the number of hardware elements required.